The phase automatic frequency control system, hereinafter referred to as PLL (foreign abbreviation Phase - Locked Loop, PLL), is an independent unit that is part of various communication equipment, satellite broadcasting and data transmission systems, as well as devices that are stable sources of signals.

The first PLL system was developed in 1930 by the French engineer Bellize. However, it became widely used in 1960 with the advent of the first integrated PLL components. There has been a traditional bias against PLL, partly due to the difficulty of implementing it on discrete components, and partly to doubts about the reliability of its operation. Over time, when highly integrated components began to appear, implementing on one chip almost all the necessary (with the exception of some external elements) PLL nodes, this system, with proper and correct design, became a fairly reliable and noteworthy node.

The PLL system can be thought of as a negative feedback system containing a forward gain G(s) and a feedback gain H(s), as well as a value e(s) characterizing the difference signal between the input signal Vi and the circuit signal feedback V 0 .

The transfer function of the closed loop of the OOS circuit (Fig. 1) will have the form:

where, G CL - closed loop transmission coefficient (from Gain Closed Loop).

Where - complex number, characterizing the circular vector, and is the circular frequency.

The PD (Phase Detector) phase detector compares two frequency signals and generates an output signal proportional to their phase difference. This difference signal is an error signal that characterizes the stability of the system, and in steady state its value tends to zero. In other words, the system is stable when the value of e(s) is zero. Hence, this system, and accordingly the PLL system, is an automatic control system or tracking system, and the measure of frequency control is the phase difference between the input (reference) signal and the feedback circuit signal.

Let us now consider the standard basic PLL model (Fig. 2) and its components:

• phase detector PD and current source CP (Charge Pump);
• loop filter, or low-pass filter with transfer function Z(s);
• voltage-controlled oscillator VCO (Voltage-Controlled Oscillator);
• divider in the feedback circuit with division coefficient N.

In a phase detector, as mentioned above, two frequency signals are compared and an output signal is generated that is proportional to their phase difference. When both signals are equal in phase and frequency, the error signal will be zero and the loop will be “closed.”

The following equation can be given to characterize the value of the error signal e(s):

when e(s) = 0,

this implies

When F 0 N·F ref , a difference periodic signal is generated at the output of the phase detector, which is then fed from the output of the current source to a low-pass filter.

This amplified and filtered phase error signal in the form of a control voltage will in turn drive the VCO whose frequency will be increased or decreased as needed by a value of K v V, where K v is the sensitivity of the VCO in MHz/V and V is the change in voltage at the VCO input. This will continue until the value of e(s) becomes zero and the circuit is blocked. Therefore, the VCO converts the input voltage it receives into its time derivative of phase, i.e., frequency. Thus, the current source and voltage-controlled generator serve as an integrator, which, upon detecting an error signal, adjusts the value of the output frequency so that the value of this error is reduced to zero. Due to integration, a phase shift of 90º appears in the control loop. Thus, the integrator included in the OOS circuit circuit introduces an additional phase delay of 90º and at frequencies where the gain is equal to unity, it can cause self-excitation. One solution is not to include components in the control loop that introduce additional phase lag, at least at frequencies where the gain is close to unity.

To clarify the situation somewhat, let's go back a little. The VCO frequency can be controlled by applying an appropriate voltage to its input. Here, it would seem, you can do the same as in any amplifier with feedback - introduce a control loop with a certain transmission coefficient, as is done when designing circuits using operational amplifiers. But there is one important difference: in circuits based on operational amplifiers, the value controlled by feedback coincided with the value measured to generate the error signal, or was at least proportional to it. For example, voltage amplifiers measure the output voltage and adjust the input voltage accordingly. The situation is somewhat different for the PLL system, since here we measure the phase and adjust the frequency, that is, as mentioned above, integration occurs, due to which the same phase shift appears. However, it should be noted that op-amps have a 90º phase lag over almost their entire frequency range, but they still work well.

In order not to include elements in the circuit that introduce additional phase lag, we can propose and analyze one of the options for constructing a control loop, the so-called “first-order circuit,” in which an operational amplifier acts as a current source, but a low-pass filter is excluded from the circuit. With this design of the circuit, the VCO input is directly connected to the output of the current source on the operational amplifier, which does not allow smoothing out noise and fluctuations of the input signal, since this circuit does not have the so-called “flywheel” property, which is ensured by the introduction of low-pass filtering. In addition, the "first order loop" does not maintain a constant phase relationship between the reference signal and the VCO signal for the very reason that the output of the current source is directly connected to the VCO input. From all that has been said above, it can be assumed that “first order loops” are not suitable for constructing PLL control loops.

The next approach is to use a "second-order loop" that introduces additional low-pass filtering. Such a circuit has the necessary “flywheel” property, thereby smoothing out interference and fluctuations of the input signal; in addition, it reduces the capture band, when it enters it, the VCO frequency begins to stabilize by the PLL system. There is also a holdband, that is, the maximum detuning band of the VCO, in which the closed loop PLL stabilizes the VCO frequency. The width of the capture and hold bands depends precisely on the type of frequency-phase response of the low-pass filter and the overall transmission coefficient of the control loop. In a properly designed PLL system, the hold band is greater than or equal to the capture band, the system is stable and does not self-excite. It should also be noted here that with the introduction of low-frequency filtering, the acquisition time also increases slightly, which characterizes the speed of entering into acquisition and maintaining the PLL system in the tracking mode during a sharp change in frequency. Analyzing the above, we can conclude that “second-order circuits” are suitable for the PLL system, which provide small fluctuations in the phase of the output signal, and also have some memory or “flywheel” properties.

The overall transfer function for the PLL can be represented using the expression G CL for the negative feedback system:

Here we introduce the additional concept of Forward Gain, denoted by G, as a coefficient characterizing the gain in the forward direction, and the concept of Loop Gain, denoted by GH, as the loop transmission coefficient.

When the value of GH is greater than one, we can say that the loop is closed, and the transfer function for the PLL system with division factor N has the form:

In Fig. Figure 3 shows the dependence of the VCO output frequency on the change in input voltage.

Before we begin to consider methods for synthesizing signals, it is advisable to consider a somewhat abstract model (Fig. 4) showing the process of forming a sequence of an Integer data stream.

In Fig. 4 are marked:

At the initial launch of the system, that is, when i = 1 and n = 0, P 0 will have some fixed value, which, “passing” through the divisors M and N, will give us the value 1. In the first step, nothing was added to the value of the divisor N, since for i = 1 n = 0. In the second step, for i = 2 and n = 1, we increase the value of the divisor N by n and so on. An indispensable condition is a constant value at all steps of the cycle. It would seem that everything is simple and clear, but by analyzing the entire process, we can derive the following expressions, which can be useful in analyzing the operation of real synthesizers.

(lab 2, layout with electronic integrator)

Goal of the work:

1) familiarization with the functional elements of the PLL system and the principle of its operation;

2) study of accuracy depending on the structure and parameters of the system;

3) study of the possibilities of changing the dynamic properties of the system using the method of sequential correction.

Description of the laboratory setup

The laboratory setup consists of a prototype PLL system, a harmonic signal generator and an oscilloscope. The PLL system in its simplest configuration contains a phase discriminator (converts the phase difference of two signals into a control voltage), correction circuits and a controlled generator (a voltage-controlled reactive element is included in the driving circuit of this generator). If the input and output signals of the PLL system are out of phase (or frequency), then the phase discriminator produces a control voltage of the corresponding sign, under the influence of which the parameters of the timing circuit of the controlled generator change and, accordingly, the frequency (and phase) of the output signal changes so as to reduce the initial upset. Without taking into account the nonlinearity of the static characteristics of the functional elements and the inertia of the phase discriminator, the transmission function of the PLL system in the open state can be represented as:

where is the transfer function of the correction circuit; - gain.

In an automatic control system of the 1st order of astatism, the dynamic tracking error depends on the rate of change of the influence (in our case, the phase) and the system gain:

(1)

where is the residual phase tracking error in degrees (it is useful to consider the phase as a dimensional value); – initial frequency detuning of generators [Hz].

There are 3 options for turning on the simplest PLL system (switch S1):

Without correction ( =1);

;

With sequential correction of the form: ,

Moreover, the time constants of the correction circuits T 1, T 2 and T 3 depend on the values ​​of resistors and capacitances indicated on the layout.

The frequency and phase relationships of the signals of the controlled and external generators are observed using Lissajous figures on the oscilloscope screen. To measure the tracking error, a phase shifter is used, connected at the output of the controlled oscillator. First set the “Detuning” knob of the external oscillator to position “0” and in the open state of the PLL system (position 1 of switch S1) perform a manual rough adjustment of the frequency of the external oscillator according to the final result (Lissajous figure - ellipse). Then the tracking ring is closed and, with the help of a phase shifter, the Lissajous figure is converted to a form convenient for observation (a line or a “figure of eight”). Subsequently, the frequency of the external generator is changed using the “Detuning” knob. A smooth change in the frequency of the input signal affects the tracking error, which leads to deformation of the Lissajous figure. By returning the figure to its previous position using a phase shifter, you can measure (on the phase shifter scale) the amount of residual error.

It should be borne in mind that the real dependence, due to the nonlinearity of the static (discriminatory) characteristic of the phase discriminator, is described by a nonlinear odd function. In this case, it is experimentally possible to obtain only a fragment of the dependence, on which a linear section should be identified for calculating the coefficient.

For a qualitative assessment of the speed and degree of oscillation of transient processes in the PLL system, a phase-shifting circuit is provided in the input signal circuit, turned on by the “Phase Jump” toggle switch.

A fully equipped PLL system additionally contains an electronic integrator: a “motor equivalent” is connected.

Work assignment

1. Turn on the generator, breadboard and oscilloscope.

2. Open the PLL system (switch in position 1).

3. Set up an oscilloscope to observe Lissajous figures.

4. By changing the oscillator frequency, ensure that the frequencies of the external oscillator and the controlled oscillator of the PLL system coincide (an ellipse on the oscilloscope screen). Close the PLL system (switch in position 2). Measure the holding band of the PLL system.

5. Set the “generator frequency” knob to the middle position (see paragraph 4). Using a phase shifter, fix the position of the ellipse, imagining it as a line or a figure eight. By changing the frequency of the generator (the “detuning” knob), and measuring the increment of the phase shift using a phase shifter, construct a relationship (you should get an odd function). To construct a graph, 3-5 points are required when the frequency is detuned in one direction and the same number of points in the other.

6. For the linear section of the dependence, determine the gain using formula (1). This value must be agreed upon with the teacher.

7. Using the obtained value, construct asymptotic logarithmic characteristics for 3 options for switching on the PLL system of the first order of astatism (construct all LCHs on one graph for ease of comparison; the parameters of the correcting elements are indicated on the layout). Using logarithmic characteristics, evaluate the quality of transient processes.

8. Qualitatively evaluate transient processes in the PLL system (for this purpose, the “phase jump” toggle switch is used).

9. Turn on the “equivalent engine” and repeat steps 4-6 (when changing the generator frequency, take into account the long-term recharge of the electronic integrator capacity). Draw the circuit of the electronic integrator and calculate its transfer function (in general form).

1. Functional diagram PLL systems, circuits of correcting elements indicating the values ​​of resistors and capacitances, circuit of an electronic integrator, open-loop system transfer functions for all options under study.

2. Table and graph of dependence, calculation and time constants of corrective elements.

3. Asymptotic LC for 3 options for constructing a PLL system of the first order of astatism.

4. Comparative characteristics transition processes and their explanation.

5. Holding bands of the studied PLL systems.

6. Structure of the shaping filter for the situation Δf=const.

3.4. Control questions

1. How do the functional elements of the PLL system and the entire system work?

2. What parameter of the input signal is informative for the PLL system?

3. What form does the structure of the shaping filter have in the case of Δf(t)=0, Δf(t)=const, Δf(t)=vt? What is the structure of the agreed ACS?

4. How do the properties of the PLL system change with increasing (decreasing) gain?

5. For what purpose are corrective elements included in the PLL system of the first order of astatism?

6. How do the properties of the PLL system change with an electronic integrator?

The PLL system (phase-locked loop system), as its name suggests, is an automatic control system (slave system), the tuning frequency of which is determined by the frequency of the control signal, and the mismatch signal is the phase difference between the control signal and the feedback signal. Due to the fact that tuning is carried out by phase difference, the system is astatic with respect to frequency: in steady state, the tuning frequency is exactly equal to the frequency of the control signal. Under certain conditions, the PLL system can be astatic and out of phase.

Along with the basic property of auto-tuning, the PLL system has the property of filtering and behaves, regardless of its functional purpose, as a tracking polynomial filter. The PLL system is a system with multifunctional capabilities and is used for frequency modulation and demodulation, frequency filtering (including filtering the frequency modulating function), frequency multiplication and conversion, reference vibration extraction for coherent detection, etc.

The PLL system can be analog, pulse, digital or combined (analog-pulse, pulse-digital, and so on). In an analog PLL system, there is a continuous signal characterized by instantaneous parameter values ​​at each moment in time. In a pulse system, signal parameters are characterized by discrete values, which can be instantaneous or interval. A pulse signal with instantaneous samples is, for example, a rectangular (“meander” type) signal of a controlled generator, characterized by instantaneous frequency values ​​at points of level change. A pulse signal with interval readings is, for example, a signal from a pulsed phase detector (PD), the duration of the pulses of which is determined by the measured phase interval. An interval pulse signal can cause timing and other types of distortion. A digital PLL system uses, accordingly, a digital signal, which is a discrete stream of data determined by the values ​​of quantized samples of the analog signal and expressed in a digital code. Quantized samples of a digital signal can also be either instantaneous or interval.

Below is a general engineering analysis of a PLL system with analog and pulse elements and discusses the applications of the system.

The PLL systems under consideration are widely used in microelectronic components produced by well-known companies. For example, Analog Devices uses a PLL system:

• in one- and two-channel synthesizers ADF410x/1x/5x and ADF420x/1x/5x types “Integer-N” and “Fractional-N” with programmable (tunable) frequencies up to 3.7 GHz;
• for multiplying the clock frequency in the TxDAC+ series DACs AD9751/3/5 (300 MHz), AD9772/4 (400/128 MHz), in digital (DDS) synthesizers-modulators AD9852/4 (300 MHz) and modulators AD9853/6 (168 /200 MHz);
• to multiply the frequency by k = 2 N /n times, where n is an integer from the series 1, 2, ... 2 N /2.5, - with AD9850/1/2/4 DDS synthesizers as frequency dividers in feedback circuits (for example, at N = 48 and a maximum frequency after multiplication of 300 MHz when using the AD9852);
• as a frequency modulator combined with a frequency synthesizer and a frequency demodulator combined with a frequency converter - in the AD6411 transceiver chip of the DECT system;
• as a quadrature modulator combined with a quadrature frequency converter - in the AD6523 transceiver chip, used in conjunction with the AD6524 synthesizer (also based on PLL), - in GSM and DCS systems;
• as a reference frequency source with quadrature output for the demodulator in the AD6432 GSM transceiver chip.

Texas Instruments uses the system:

• in two- and three-channel frequency synthesizers TRF2020 - up to 0.25, 0.25 and 1.2 GHz, TRF2050 - up to 0.25 and 1.2 GHz, TRF2052 - up to 0.15 and 2.0 MHz and TRF3040, which is also a modulator, - up to 0.2 and 2.0 GHz;
• for synthesizing reference frequency signals for modulators in TRF3040 and TRF3520 microcircuits;
• for clock multiplication in TMS320C54x, TMS320C62x, TMS320C67x and TMS320VC33 digital signal processors.

Motorola (Semiconductor Product Sector) uses the system in two-channel frequency synthesizers MC145181 (up to 550 and 60 MHz), MC145225 (up to 1.2 and 0.55 GHz), MC145230 (up to 2.2 and 0.55 GHz), etc. , intended for radio communication equipment of various systems.

Gran-Jansen AS (Norway) uses a PLL system in the GJRF400 (GJRF10) transceiver, operating in the frequency range 300–500 MHz, for reference wave synthesis and for analog frequency modulation.

The above list is far from complete, however, the listed microcircuits quite fully characterize the possibilities of using the PLL system.

Basic relationships

In general terms, any automatic control system, regardless of its purpose, contains a measuring device with a subtractor at the input and a control object, the output of which is connected to the subtractor. In the subtractor, the control value and the controlled value (from the output of the controlled object), which is the feedback value, are compared. Along with the concepts of control and controlled quantities, we will use the concepts of input and output, which determine the functional purpose of the system. In general, the input and output quantities are not always control and controlled (in the specified understanding of these terms). Transfer function of the system -

K(p) = x out /x in = K pr (p)/, (1)

where x out and x in are output and input quantities, and K pr (p) and K arr (p) are the transfer functions of direct transmission circuits (from input to output) and negative feedback (from output to input), p is the operator Laplace (the plus sign in the denominator means that the feedback is negative). The input quantity can be supplied to the input of any element, and the output quantity can also be taken from the output of any element of the system.

Rice. 1

In Fig. Figure 1a shows a diagram of the simplest PLL system containing a phase detector PD (measuring device), filter F and a controlled generator UG (control object). FD and UG are mandatory elements of the system, and a filter that affects its dynamic (frequency) properties may be absent. The control variable is the frequency w 0 + D w input of the alternating voltage at the PD input, the components of which are: w 0 - the reference frequency of the system and D w input - the change in frequency, which is the input value affecting the system. The feedback value is the frequency of the oscillator, equal to w 0 + D w arr, where D w arr = D w input – pD j, and pD j and D j are changes in the frequency and phase at the PD input caused by D w input. In Fig. Figure 1b shows a diagram of a variant of the system, which differs in that only the reference frequency w 0 acts at the PD input, and the input value of the system is the voltage uin at the input of the CG, applied through the “+” adder. Input and output quantities D w in and u out in Fig. 1a determine the purpose of the system - a frequency demodulator, and u in and w 0 + D w out in Fig. 1b - frequency modulator. Functionally, the adder in Fig. 1b is a subtractor, since negative feedback operates in the system loop.

Despite the fact that the control variable in the PLL system is frequency, in the PD it is not the frequencies that are compared, but the phases of the voltages at its input. As a result, the phase difference, which is the integral of the frequency difference, is equal to D j = (D w in - D w arr)/p (Fig. 1a) or D j = -D w out /p (Fig. 1b), and the transfer function PD, respectively, K PD (p) = K PD /p, where K PD is the transmission coefficient with the dimension V/rad. The phase difference at the PD input, in addition to D j, may contain an initial constant component j 0, at which at the PD input j = j 0 + D j. The component j 0 is the integration constant and is determined by the choice of the PLL system mode taking into account the detector characteristic of the PD.

Transfer function of the PLL system according to the circuit in Fig. 1a, used for frequency demodulation, is characterized by the expression

K BH (p) = U out / D w in = K 0 /, (2)

where u out is the voltage at the filter output (output voltage of the demodulator), due to the change in frequency at the input D w in, K 0 = 1/K UG is the system transmission coefficient (in this case, at the “zero” frequency), t 0 = 1 /K FD K F K UG is the “own” (without taking into account k F (p) filter) time constant of the system, K UG is the transmission coefficient of the controlled generator (with the dimension (rad/s)/V), and K F and k F (p) - constant and frequency-dependent multipliers of the filter transfer function K Ф (p) = K Ф k Ф (p). In the absence of a filter, that is, with K Ф (p) = 1,

K BH (p) = K 0 /(1 + rt 0), (3)

where t 0 = 1/K FD K UG. Transfer function (3) is a function of a 1st order polynomial low-pass filter. In general, the order of the PLL system is equal to one plus the order of the applied filter Ф (integrating circuit or low-pass filter).

Transfer functions (2) and (3) are “external” functions of the PLL system, conditioned by the given input and output of the system. The main function of the system is

K D j (p) = D j /D w in = /, (4)

where D j is the change in the phase difference at the PD input, due to the change in the control frequency D w input, and 1 + pt 0 /k Ф (p) in the denominator of the function is the system polynomial (according to the terminology in the theory of polynomial filtering), present in all “external ” transfer functions, including in (2), differing in expressions in the numerator.

Elements of the PLL system

As has already been said, the main (mandatory) elements of the PLL system are the FD and the UG, which in the systems under consideration can be analog or pulsed. In addition, the PLL systems under consideration may include analog filters, frequency dividers with pulse or analog outputs, mixers, etc.

Phase detectors. In Fig. Table 2 shows the detector characteristics of the most used PDs:

• sinusoidal characteristic of phase detection of multiplying and commuting analog amplitude-phase detectors (APD) (Fig. 2a);
• sawtooth characteristic of the trigger pulse PD (Fig. 2b);
• triangular characteristic of the multiplying pulse PD (Fig. 2c) (its version is also shown in Fig. 2d);
• sawtooth characteristic of phase detection of a bipolar trigger pulse frequency-phase detector (PDF) (Fig. 2d).

Rice. 2

First of all, we note that the detector characteristics are static, in which the dynamic error inherent in pulsed PDs does not appear. In analog PDs, the instantaneous phase difference is measured

D j (t) = j 1 (t) - j 0 (t) = d j (t),

where, in the simplest case, j 1 (t) = w 0 t + d j (t) and d j (t) are the phase and modulating phase change of the detected signal, and j 0 (t) = w 0 t is the phase of the reference oscillation. We emphasize that we are talking about the current difference between the instantaneous values ​​j 1 (t) and j 0 (t), simultaneously counted at the same instants of time t.

In pulsed PDs, unlike analogue ones, the phase interval D j (D t i) is measured, proportional to the time interval D t i = t 0i – t i, where t 0i and t i are different moments in time at which the phases of the signal j 1 (t i) = w 0 t i + d j (t i) and reference vibration j 0 (t 0i) = w 0 t 0i are equal. Typically, points with zero instantaneous values ​​of the sinusoid are taken (Fig. 3a), which ensure the formation of input and, accordingly, output PD pulses shown in Fig. 3b-d. If j 1 (t i) and j 0 (t 0i) are equal, the time interval is D t i = d j (t i)/w 0, and the phase interval is

D d (D t i) = w 0 D t i = d j (t i), (5)

According to (5), the measured phase intervals D j (D t i) are numerically equal to the desired instantaneous phase differences d j (t i). However, it should be taken into account that in the current time scale the sequence of interval readings is equivalent to the sequence of instantaneous readings at discrete points t j = t i + D t i /2 - instead of the points t i to which they correspond. As a result, the phase will be measured with a time error D t i /2:

D j (t i) = d j (t i + D t i /2)

Let us consider the detector characteristics of the PD. The characteristics of the multiplying analog NPD shown in Fig. 2a, is determined by the expression

U NPD = K NPD Ucosj, (6)

where U is the amplitude of the detected voltage, j is the phase difference between the detected and reference voltages, and K APD is the detection coefficient depending on the amplitude of the reference voltage, which therefore must be constant. Both voltages, detected and reference, are sinusoidal. Expression (6) is also valid for a switching analog APD using a detectable sinusoidal voltage switch controlled by a reference square wave voltage. In the general case, an analog APD, according to (6), detects not only the phase difference, but also the amplitude of the detected voltage U, which is why it is called amplitude-phase. In accordance with the above, during phase detection, the amplitude of not only the reference, but also the detected voltage should be maintained constant. The dependence of u of the APD on U is a disadvantage of the detector if it is used as a phase detector (a commutating APD can also be used as a synchronous amplitude detector). Another disadvantage of the analog NPD is the nonlinearity of its characteristics, and therefore its narrow sections are used for detection, for example, from p /4 to 3p /4 or from -3p /4 to -p /4. When introducing a phase shift j 0 = -p /2, the operating point on the NPD characteristic (Fig. 2a) is shifted to the left by the specified angle, and the argument j in (6) is replaced by a detected phase change D j . As a result,

U NPD = To NPD UsinD j = To NPD UD j, (7)

where the second (approximate) part of the expression, proportional to D j, is for a section of the phase range D j from -p /4 to p /4.

Note that an analog multiplier, which has the above disadvantages (when used as a phase detector), is widely used as a mixer in frequency converters, which require high “purity” of the converted frequency spectrum, and for which analog multipliers are ideal elements.

As a multiplying pulse PD with the characteristic in Fig. 2c (inverse to the characteristic in Fig. 2a) they usually use an “Exclusive OR” microcircuit, but it has unstable output levels “0” and “1”, and therefore it is of little use for directly measuring the phase difference. Therefore, an analog multiplexer with a two-bit address input is used as PD inputs. Such a multiplexer can be imagined as consisting of an “Exclusive OR” phase-detection microcircuit and an output switch controlled by it. The use of a commutator and commutated precise voltages ensures that precise PD characteristics are obtained. In addition, depending on the choice of switched voltage levels, it is possible to change the value of the conversion (detection) coefficient, as well as vertically shift the characteristic and its inversion. In Fig. Figure 2d shows the shifted characteristic due to the switched voltages -E and E (instead of 0 and 2E, which correspond to the characteristic in Fig. 2c). In addition, the characteristic in Fig. 2d is shown as a function of D j for j 0 = p /2 (similar to (7) for APD):

U FD = K FD D j, (8)

Characteristic (8) is linear in the operating range from -p /2 to p /2.

Multiplying pulse PDs are widely used in PLL systems. Let us note the following features in the operation of PDs: in pulsed PDs constant levels of “extraneous” sources are switched, while in switched analogue NPDs the detected voltage is switched. And, in addition, in pulsed PDs the switch is controlled by pulses from the output of the multiplier, while in analog APDs the switch is controlled by the reference voltage.

The characteristic of a trigger pulse PD, for example, of the RS-trigger type (Fig. 2b), differs from the characteristics considered in the twice larger phase range - from 0 to 2p and the slope of the working section of the characteristic of only one sign - positive or negative (the positive slope of the characteristic shown in Fig. 2b, can be changed to negative by “reversing the polarity” of the trigger inputs or outputs). To increase the accuracy of the characteristic, like “Exclusive OR”, a commutator with switched precise voltages can be turned on at the output of the trigger. It is significant that the FD under consideration is a trigger one and operates “on the front,” while multiplying FDs operate “on the duration.” For this reason, the trigger (trigger) PD has less noise immunity, and, in addition, its use leads to transient processes at the beginning of demodulated messages. The phase characteristic of the PPD is a combination of two characteristics of the trigger pulse PD, added with opposite signs (Fig. 2e). In modern PFDs, widely used in frequency synthesizers, measures have been taken to ensure high-quality “matching” of two characteristics, in which there is practically no detection noise (the so-called low-noise PFDs). The phase range of the PFD is from -2p to 2p. The polarity of the PPD output pulses is determined by the sign, and the duration, as in a conventional trigger PD, is determined by the value of the measured phase difference (phase interval). Typically, PFDs have a current output (with a high output resistance), which turns out to be convenient when building systems with passive proportional-integrating circuits as a filter. In steady-state mode, when using a PLL system with phase astatism, the duration of the pulses at the PFD output is zero (there are no pulses). This mode is the main one when using PFD in frequency synthesizers. When there is a frequency mismatch, the PFD operates as a frequency detector with a bipolar relay detection characteristic that depends on the sign of the mismatch.

Rice. 3

The characteristics of PDs of all types are periodic, which is due to the periodicity of changes in the phase angle. The positive or negative slopes of the analog or multiplying pulse PD characteristics determine the plus or minus sign of the PD transfer function, which is automatically selected by the PLL when it is turned on. At the same time, the system provides negative feedback taking into account the signs (plus or minus) of the transmission coefficients of other elements. In contrast to the sinusoidal or triangular characteristics of the PD, the sawtooth characteristics of the trigger PD and PPD require a preliminary selection of the sign of the slope, which, as mentioned above, can be changed by “reversing the polarity”.

Typically, a PD, as well as a detector of any kind, is understood as an element consisting of two parts - detecting and filtering. When constructing a PLL system, its first, detecting part is used as a PD, and the applied filter is considered as an element of the system. The PD output signal contains a useful component, proportional or almost proportional (depending on the PD type) to the detected phase difference, as well as high-frequency components that appear in the form of ripples and are usually subject to filtering. The ripple spectrum is determined by a carrier with frequency doubling (for multiplying PDs and switching PDs with doubling) or without frequency doubling (for switching PDs without doubling and trigger PDs).

In addition to the above, we note that the input signals of analog and multiplying pulse PDs must be sinusoidal or rectangular, respectively, with a duty cycle of 2. For trigger PDs, compliance with the duty cycle is not required, but it should be taken into account that the phase difference between the pulse edges that trigger and trigger reset.

Controllable generators. As already mentioned, the OG in the PLL system can be analog or pulsed (like the PD). An analog oscillator can be a narrow-band high-frequency (hundreds of MHz, units of GHz) transistor generator with an oscillating circuit, which uses voltage-controlled varicaps (varactors). The generator does not require the E0 bias shown in Fig. 1a,b. Its mode is provided by its own bias circuit. The output voltage of the generator is sinusoidal, but when using a comparator it can be square-wave (pulse).

A wideband voltage-frequency converter with continuous integration and charge balancing, also known as a PFM modulator, can be used as a pulsed UG (with a frequency of up to several MHz). The frequency of such a UG (its instantaneous discrete values) is proportional to the converted analog voltage (its instantaneous values ​​at the same time reference points). An example of the UG under consideration could be the AD650 and AD654 converters from Analog Devices. There is a type of UG with synchronization of the output signal frequency by clock pulses (AD652, AD7741/2). This type of generator is similar to a sigma-delta modulator and is intended for use in systems with digital conversion.

Rice. 4

In Fig. Figure 4a shows a block diagram of a pulsed UG (without synchronization), and Fig. 4b - stress diagrams on its elements. It also shows the voltages on the elements of a filterless PLL system with the considered pulsed UG and multiplying pulsed PD. In Fig. 4a,b: Uin - voltage at the control input of the PD; U arr is the feedback voltage at the other input of the PD, which is the output voltage of the UG (U UG); U vxUG - voltage at the input of the UG, which is the output voltage of the FD (U FD); U int, U comp and U single are the voltages of the integrator, comparator and monovibrator as part of the control unit. Voltage diagrams clearly illustrate the process of operation of the control unit and the PLL system as a whole. It can be seen, in particular, that UvxUG is “filtered” in the integrator: the result of integration, completed by the operation of the comparator, is determined by the integrated voltage area U inxUG and does not depend on its shape.

Frequency dividers. Frequency dividers, included in the feedback loop between the control unit and the PD, ensure frequency multiplication by the PLL system at the output of the control unit. Conventional counters or specially created dividers for frequency synthesizers (in combination with counters connected at the input of the PLL system) can be used as dividers. Frequency synthesizers provide fractional frequency multiplication with high resolution, implemented through software tuning. Special frequency dividers used in synthesizers include dividers of the “Integer-N” and “Fractional-N” types (with integer and fractional division coefficients, respectively). The first of them are widely used in frequency synthesizers, the second are new, providing higher parameters for synthesizers. The above-mentioned digital synthesizers (DDS) with analog output can also be used as frequency dividers.

Typically, devices using a PLL system are produced in the form of microcircuits on a single chip. External filters are the ones discussed below, as well as frequency-setting circuits of controlled generators containing inductive elements, capacitors and varicaps (varactors).

PLL operating mode

Rice. 5

In Fig. Figure 5a shows a diagram of the PLL system (in a simplified form without a filter) with the designation of quantities characterizing the operating mode of the system (for an amplifier, such a mode would be called the DC mode). In Fig. 5a, the control variable is the frequency w0 at the input, which, thanks to phase-locked loop, is equal to the frequency of the UG, and the control voltage of the UG and, accordingly, the output voltage of the FD are equal to E 0 = w 0 /K UG. The initial phase difference at the PD input with the characteristic in Fig. 2c (multiplying pulse PD with switched voltages 0 and 2E) is equal to j 0 = E 0 /K PD = = w 0 /K PD K UG = w 0 t 0 . Usually j 0 = p /2 or -p /2 is selected, at which the operating point is in the middle of the linear section of the characteristic.

In Fig. Figure 5b shows a variant of the circuit with an external bias source E0, corresponding to the circuit in Fig. 1st century In this embodiment, the voltage at the PD output is zero, but the initial phase, as in the previous case, is equal to j 0 = p /2 or -p /2. The latter is ensured by PD switching voltages equal to -E and E, and corresponds to the characteristic in Fig. 2g. In reality, in the diagrams in Fig. 5a,b, the initial phase difference and the output voltage of the PD will have slight deviations from the indicated values, which is due to the automatic tuning of the system to compensate for the influence of deviations of the PD and HC parameters and the voltage E0 of the external source from the specified nominal values.

Despite the complexity, the diagram in Fig. 5b (Fig. 1c) may be more preferable for the following reason. The fact is that the time constant t 0 determines, along with k Ф (p), the dynamic properties of the system, and therefore it should be possible to select its required value. At the same time, for the circuit in Fig. 5a, according to the above expression for j 0, the quantities t 0 and j 0 are interrelated, and a change in t 0 will entail a change in j 0. As a result, the specified mode of the PD and the PLL system as a whole will change. Scheme in Fig. 5b is free from this drawback, and t 0 can be selected independently of j 0.

Frequency properties of the PLL system

Transfer function (3) is a 1st order function. Applying a filter to the PLL changes the dynamic properties of the system. The system polynomial (the polynomial in the denominator of the transfer functions) determines the order, type of approximation, and frequency range of the filtering, and the term or polynomial in the numerator determines the type of filtering (low-pass, high-pass, or bandpass filtering) and the transfer coefficient.

Rice. 6

2nd order PLL systems typically use one of the 1st order filters shown in Fig. 6 (note that the generally accepted name “filter” in this case is conditional; it would be more correct to consider them frequency correction circuits):

• integrating filter (IF) (Fig. 6a) with transfer function K Ф (p) = U output /U input = 1/(1+p t Ф) = k Ф (p) at K Ф = 1, where t Ф = RC - filter time constant;
• proportional integrating filters (PIF) (Fig. 6b,c) with transfer function K Ф (p) = U output /U input = = (1 + p t Ф1)/(1 + p t Ф) = k Ф (p) at K Ф = 1, where t Ф = RC, t Ф1 = R2C, R = R1 + R2;
• proportional-integrating circuits (PI) (Fig. 6d,e) with transfer function K Ф (p) = U out / I input = K Ф k Ф (p), where K Ф = R, k Ф (p) = 1 + 1/p t Ф1 , t Ф1 = RC.

The PI circuit differs from the IF and PIF in that the source of its input signal is a current source Iin with an infinitely large resistance. In a PLL system, the PI circuit is implemented, for example, by using a PI operational amplifier as a parallel negative feedback circuit. The transfer function of the circuit with the amplifier is equal to K Ф (p) = -(K Ф + 1/p t Ф) = -K Ф k Ф (p), where K Ф = R/r, t Ф = rC, r is the current-setting resistance of the circuit , switched on at the input of the amplifier, and k Ф (p) - according to the PI in Fig. 6d,d. The minus sign, determined by the inverting connection of the amplifier, must be taken into account in the phasing of the PD, if the PD has a sawtooth characteristic. Note that tФ is the “physical” time constant of the PI circuit, as well as the PIF, while t Ф1 is a conditional time constant, convenient for writing mathematical expressions. The transfer function of the PI, determined by K Ф + 1/p t Ф, in contrast to the PIF, consists of two functions - proportional KФ and integrating 1/p t Ф. K Ф affects the quality factor and, accordingly, the stability of the system (at KФ --> 0 the PLL system is unstable), and the term 1/p t Ф determines the integrating property of the PI, which ensures the astatism of the PLL system with respect to the phase. IN Lately Instead of an operational amplifier that provides current “power supply” to the PI, a current driver is used, which is used together with the PFD discussed above. The specified driver provides connection of the PI with its “lower” output to the “ground”. Note that, along with the simplest RC circuit in Fig. 6d, circuits of complex configuration and, accordingly, higher orders are used as PIs.

In addition to the main outputs of the filters U out, connected in the PLL system to the input of the UG, in Fig. 6b-d shows additional outputs U out*, which, along with the main ones, can be used to pick up the output signal of the PLL system. The use of additional outputs is equivalent to connecting external filters at the system output that are not involved in a closed feedback loop. The transfer functions of the filters for additional outputs, along with the functions for the main outputs, are given in the table.

The polynomial of the transfer functions of a 2nd order PLL system, as well as polynomial filters of the same order, is determined by the generalized expression 1 + p /w 0 Q + p 2 /w 0 2, where w 0 is the natural frequency of the system, known in filter theory as the frequency poles, and Q is the quality factor, which determines the type of approximation of frequency characteristics (according to Butterworth, Chebyshev, etc.). The table shows the polynomials of the functions of the PLL system with different filters, as well as the corresponding expressions Q and w 0. The table also shows the data of the main function K D j (p) (4) and the transfer function of the system when used as a frequency demodulator: K BH ^(p) - with output after the PD (before the filter), K BH (p) - after filter and KChD*(p) - when picking up a signal from the additional output of the filter. We emphasize that the operator p in the transfer functions of the PLL system is determined by the expression jW, where W is the frequency of change in the frequency at the input and, accordingly, the output voltage (for frequency modulation, this is the modulation frequency).

Analyzing the data presented in the table, the following conclusions can be drawn. The function K D j (p) of a 1st order PLL system is a low-pass filter function, and with PI it is a PF (band-pass filtering) function with a resonant frequency w 0 . The PF function of a system with PI determines the astatism of the system with respect to the phase: the transmission coefficient at zero frequency is zero. The transfer function K D j (p) of a system with IF and PIF is the total function of the low-pass filter and the PF, which can be considered as a low-pass filter function changed in the region of the cutoff frequency. Recall that 2nd order filtering is low pass filtering if the numerator of the function is a zero order term (t 0), and bandpass filtering if it is first order (pt 0 t Ф1).

The functions K BH (p) and K BH* (p) for a system with PIF are identical to the functions for a system with PI, but they are achieved at the different K D j (p) indicated above. The use of additional outputs, characterized by K BH* (p), ensures, in contrast to K BH (p), obtaining transfer functions such as low-pass filter (Fig. 6b,d) and PF (Fig. 6c,e), and K BH* ( p) of the low-pass filter type is similar to the KChD(p) of a system with an IF. A feature of the use of PIF, compared to IF, is that the required quality factor can be set by changing the ratio R2/R (t Ф1 /t 0) without changing t 0 and t Ф and, accordingly, without changing w 0.

Application of PLL system

The use of a PLL system depends on which of its elements is the input and which is the output. Let's look at the main applications of the PLL system.

Frequency demodulator. When using a PLL system as a frequency demodulator, the FM signal is fed to the PD input (Fig. 1a, c), and the demodulated one is removed, for example, from the filter output. The transfer function of the demodulator will be determined by the numerator and denominator expressions given in the table, as well as expression (2). To filter the demodulated signal with the required parameters, an additional external filter is usually used. In this case, the PLL system should be considered as the first filtering stage and taken into account accordingly when calculating the overall filter transfer function (with the required order, approximation and cutoff frequency).

Frequency modulator. When using a PLL system as a frequency modulator, the modulating signal uin(t) is supplied to the input of the CG, as shown in Fig. 1b, and the modulated one is removed from the output of the UG. In this case, the modulator itself is the UG, and the PLL system sets the carrier frequency, determined by the reference (control) frequency at the PD input. In addition, the system provides filtering of the modulated signal, determined by the selected parameters of the transfer function. In general, the transfer function of the PLL system in FM mode, in contrast to (2) for demodulation,

K FM (p) = D w out /u in = ,

where K 0 = t 0 K UG. When using mutual funds

K FM (p) = (pK 0 + p 2 K 0 t f)/(1 + pt 0 + p 2 t 0 t f); (9)

K FM *(p) = pK 0 /(1 + pt 0 + p 2 t 0 t f), (10)

Accordingly, to remove the FM signal from the main and additional outputs of the PIF (Fig. 6b). Function (9) is the total function of the PF and high-pass filter, and function (10) is the function of the PF. The second signal pickup option is more preferable for narrowband modulated signals.

Rice. 7

Frequency filters. In Fig. Figure 7a shows a diagram of a PLL system with frequency filtering of the voltage uin, and in Fig. 7b - with frequency filtering of the modulating frequency change Dwin as part of the FM signal. Both filters have the same transfer function

K f (p) = 1/,

which is a function of the low-pass filter when using the IF and the total function of the low-pass filter and the PF when using the PIF and PI. In addition, the first of the filters (Fig. 7a) can be used to pick up a signal from additional outputs PIF and PI, for which the low-pass filter and PF functions are implemented, respectively.

Phase shifter. Shown above is the dependence of the constant phase difference at the PD input on the operating mode of the PLL system (Fig. 5a,b). In accordance with this, when picking up a signal from the output of the UG, as shown in Fig. 7b, it is possible to obtain a phase shift of the output signal, for example, j 0 = p /2 or -p /2 (quadrature phase shift). The angle j 0 = p /2 is ensured when choosing the PD characteristic in Fig. 2d, and j 0 = -p /2 - during “polarity reversal,” for example, of sources E and -E. Other angle values ​​are also possible.

Frequency multiplier. Frequency multiplication by the PLL system is ensured by including a frequency divider “:N” in the feedback circuit, as shown in Fig. 7th century The frequency at the output of the UG, which is the output of the multiplier, is equal to w out = w 0 N, where N is the division coefficient of the divider. In frequency synthesizers, a frequency divider “:R” is additionally included at the input of the PLL system (not shown in Fig. 7c). As a result, w 0 = w in /R, and w out = w in N/R, where R is the division coefficient of the divider “:R”. The combined use of “:R” and “:N” dividers (with programmable division coefficients) provides frequency synthesis over a wide range and with high resolution.

The introduction of a frequency divider into the feedback circuit increases the inertia of the PLL system: t 0 = N/K FD K F K UG. Inertia can be reduced by introducing additional gain, which will compensate for the influence of N, but there is another way. Frequency synthesizers use, as indicated above, frequency dividers of the “Integer-N” or “Fractional-N” type. The latter, unlike the first, is characterized by fractional numbers of the coefficient N. Therefore, the values ​​of N for “Fractional-N” can be smaller (for example, N = 10.25 instead of 1025 for “Integer-N”) with a correspondingly larger (at the same 100 times) to the value w 0 . With a smaller value of N there will be less influence on t 0 , and with a correspondingly larger value of w 0 the conditions for filtering the PD signal arriving at the input of the UG are facilitated.

Frequency multiplication can also be implemented in a PLL with a DDS synthesizer as a frequency divider, but at lower frequencies. If for the ADF4113 synthesizer (with “Integer-N”) the synthesized frequencies are up to 3.7 GHz, then for the frequency multiplier with the AD9852 DDS synthesizer - up to 300 MHz. Frequency multiplication is sometimes combined with frequency modulation (manipulation), as, for example, in the AD6411 transceiver chip. Note that when multiplying the frequency of an FM signal, not only the carrier frequency is multiplied, but also the frequency deviation.

Rice. 8

Frequency conversion with phase-locked loop. In Fig. 8a shows a diagram of a PLL system with a built-in frequency converter containing an “X” mixer and a PF bandpass filter tuned to the frequency difference w 0 = w 1 – w 2 (AD6411 chip). The input quantity is w 1 + D w in with the carrier w 1, and the output is the voltage u out. The device in question is a frequency demodulator, in which demodulation is preceded by frequency conversion. A special feature of the device, in contrast to the usual inclusion of a converter and demodulator (without feedback), is that it automatically adjusts the system to the difference frequency w 0. It is set as a control value at the PD input.

The device in question can be used not only for demodulation, but also for frequency conversion, without picking up the demodulation signal. In this case, the converted carrier is w 2, and the signal is removed from the output of the UG, as shown in Fig. 8b. Transfer function of the demodulator in Fig. 8a

K BH (p) = K 0 /, (11)

where k Ф (p) and k PF (p) are variable multipliers of the transfer functions Ф and PF, and K 0 = 1/K УГ. In the simplest case, if the PF is of the second order with k PF (p) = ap/(1 + ap + bp 2),

K BH (p) = K 0 /

is a low-pass filter function, the order of which is reduced by one due to the multiplier ap in the numerator of the PF function. The expression for the converter transfer function is the same as for the demodulator, but with K0 = 1.

Quadrature modulation with phase-locked loop. In Fig. Figure 8c shows a diagram of a quadrature modulator based on a PLL system used in GSM and DCS radio communication systems (AD6523 chip). The loop of the PLL system shows a quadrature modulator “Mod.”, at the input of which is a frequency converter “X”. The modulator transfer function in Fig. 8v

K mod (p) = D w out /u in = K mod /, (12)

where K mod = D w mod /u input is the transmission coefficient of the modulator “Mod.”. If there is bandpass filtering in the system, it is additionally taken into account in (12) similar to (11).

Let's note the following interesting fact. In the systems in Fig. 8, mixers and a modulator are used, which are signal multipliers and, accordingly, are nonlinear elements (as, indeed, a phase detector). But for the frequencies and phases of the same signals, they are adders or subtractors. As a result, to change the frequency, the mixer and modulator are linear elements.

The use of the PLL system is not limited to the examples given. Any system whose operation is based on phase-locked loop is, accordingly, a PLL system in one form or another. The components listed above from manufacturers are typical examples of the use of a PLL system. Components using the PLL system are distinguished by their variety and high technical characteristics.

Literature

1. Phase synchronization systems with sampling elements / Ed. V.V. Shahgildyan. - M.: Radio and communications. - 1989.
2. Fomin A.A. and others. Analog and digital synchronous-phase meters and demodulators. - M.: Radio and communications. - 1987.
3. Levin V.A. and others. Frequency synthesizers with a pulse-phase locking system. - M.: Radio and communications. - 1989.
4. Curtin M., O'Brien P. Phase Locked Loops for High-Frequency Receivers and Transmitters // Analog Dialogue, Analog Devices, 1999, Vol. 33, No. 3, 5, 7.
5. Fague D. OthelloTM: A New Direct-Conversion Radio Chip Set Eliminates IF Stages // Analog Dialogue, Analog Devices, 1999, Vol. 33, No. 10.
6. Golub V. GJRF10 transceiver from Gran Jansen AS // Chip News. - 1998. - No. 4. - P. 30–32.
7. Moschitz G., Horn P. Design of active filters. - M.: Mir. - 1984.
8. Golub V.S. Instantaneous and average frequency of oscillations and integrating FM and PFM modulators // Radio engineering. - 1982. - t. 37. - No. 9. - P. 48–50.
9. Golub V. A look at the sigma-delta ADC // Chip News. - 1999. - No. 5. - P. 23–27 (as amended in No. 8, p. 48).
10. Technical Brief SWRA029: Fractional/Integer-N PLL Basics / C.Barrett. - Texas Instruments, August 1999.
11. Golub V.S. Equivalent circuit of the PLL system // Izv. universities Radioelectronics. - 1994. - t. 37. - No. 8. - P. 54–58.

An Internet search for a device that matches the title of this article was unsuccessful. On the Forums they believe that such a device cannot be created. However, at present, a prototype of a 16-bit ADC has been manufactured and tested on the ATmega 16 microcontroller (MCU), which is part of a commercial product.

Description of the scheme

Figure 1 shows a schematic diagram of the ADC drawn in the Proteus 7.7 program. Programming of the MK was performed in IAR Embedded Workbench using the “Training Course” author: Pashgan on the website. The operation of the ADC was checked in hardware. Simulation of ADC operation in Proteus failed, the reason is described below.

Fig. 1 Schematic diagram of a 16-bit ADC.

A detailed description of all elements (chips) of the circuit can be found on the Internet; let’s consider the purpose of each element in the ADC circuit.

Microcontroller ATmega 16

The MK signal diagram is shown in Figure 2. The MK must generate 2 clock signals of a fixed frequency of 122 Hz (16 MHz/65536 = ~122 Hz). The timer-counter MK T1 operates in “normal mode”, without a prescaler, with switching the state of outputs OC1A and OC1B, and generates rectangular pulses of the “meander” type at pins 18 and 19, which are shifted by 90°. To do this, a number equal to half the maximum value of the T1 timer code is written to the comparison register OCR1B. At the output of the D4B chip (exclusive OR logic element), rectangular pulses F1 of double frequency (244 Hz) are generated, which are supplied to the first input (pin 14) of the Phase Detector (PD) of the Phase Locked Loop (PLL) chip D2. The leading edge of the F1 pulses always coincides with the zero code of timer T1. In a real circuit, due to delays in the circuit elements, the initial offset of the zero code does not exceed 5 units of the least significant bit (EMP) of the T1 timer and must be taken into account when generating the ADC conversion result. In the ADC layout, the delay in the MK is 2 EMP (0.125 µs) in 2 elements D4 – 3 EMP (0.15 µs)

Rice. 2. Signal diagram of MK and microcircuits D2 and D4.

If the ATmtga 16 MCU is set to the “capture” mode of the T1 timer-counter state (“capture”), and rectangular pulses with a frequency of 244 Hz are supplied to the “capture” input ICP1, the leading edge of which will lag in phase behind the leading edge of the F1 pulses, then The 16-bit phase shift code between the leading edges of the F1 and F0 pulses will be read into the 16-bit register ICR1. The choice of symbols for the F1 and F0 signals is associated with the operating logic of the pulsed PD microcircuit D2 74HC4046. The leading edge of the F1 pulse sets the PD output (Tx pin 15 D2) to the “Log.1” state, and the leading edge of the F0 pulse to the “Log.0” state. In Proteus, the symbol for pin 15 of the D2 chip “ZENER” differs from the designation “PHASE COMPARATOR III”, which is given in the manual for the use of the chip. In the diagram of Figure 1, this error remains, because Failed to fix the graphics for library item 74HC4046.

To solve the problem: create a 16-bit ADC on an 8-bit AVR, you need a device that must convert an analog signal (for example, voltage) into the duration of Tx pulses (phase shift between pulses F1 and F0), the average voltage of which is equal to the input voltage Ux. This device is described in detail in the article “PLL-stabilized voltage-to-pulse-width converter” in the magazine. Further in the description, materials from this article will be used, which are necessary to explain the principle of operation of the ADC. To display the results of the ADC conversion, an alphanumeric LCD display TC1602-A, D5 is used in Figure 1.

Chip 74НС4046 and operational amplifier ½ package D3 (AD823)

The 74NS4046 microcircuit and an operational amplifier (op-amp) form a PLL circuit, the input of which receives a pulse signal F1. The PLL is an automatic control system with Negative Feedback (NFB), which adjusts the frequency of the internal Voltage Controlled Oscillator (VCO) so that its frequency Fo is equal to the frequency of the input signal F1, Figure 3. The adjustment is carried out due to the presence of negative feedback. The output signal of the VCO, rectangular pulses with frequency F0, is compared at the Phase Detector (PD) with the input signal F1, the phase error signal after filtering and amplification is used to adjust the output frequency of the VCO.

Fig.3 Functional diagram of PLL.

The PLL circuit is similar to the Operational Amplifier (OPA) circuit, with the only difference being that the input variable is the oscillation phase, and the frequency (rate of phase change) is the feedback signal.

Rice. 4. PLL block diagram.

Due to the fact that tuning is carried out by phase difference, the system is astatic with respect to frequency: in steady state, the tuning frequency is exactly equal to the frequency of the input signal (Fo=F1), and the phase shift is set such that the low-pass filter output voltage (Ugun) ensures equality of frequencies. Under certain conditions, which depend on the type of low-pass filter, the PLL system can be astatic and out of phase. More detailed description The PLL, with the conclusions of the formulas, can be found on the Internet, and in books.

The PLL system is mainly used for frequency and phase modulation and demodulation, frequency multiplication and conversion, frequency filtering or reference waveform extraction for coherent signal detection. Typically, the input signal in PLL devices is frequency. A PLL is a feedback loop control system in which the control parameters are the frequency or phase of the signal, rather than the magnitude of its voltage or current. The proposed device uses a non-standard PLL switching circuit with an additional voltage regulation parameter.

Let us introduce into the standard PLL circuit a generator G of the F1 signal with a fixed frequency and a comparison element at the input of the low-pass filter, which must compare the input voltage Ux with the output signal of the PD. Let's change the design of the PLL functional diagram. Figure 5 shows a functional diagram of a converter of an analog signal (voltage Ux) into pulse duration Tx, Pulse Phase Modulation (PPM) with PLL.

Phase Modulation (PM) is one of the types of oscillation modulation, where the phase of the carrier oscillation is controlled by an information signal (periodic change in the oscillation phase according to a certain law; slow compared to the oscillation period). From the definition of PM it follows that there is a sinusoidal signal generator in which the phase of the output signal changes over time. This type of modulation is used in radio engineering to transmit information. PM is usually considered for sinusoidal signals.

Fig.5 Functional diagram of the converter of the analog signal Ux into pulse duration Tx.

The proposed device uses phase modulation of pulse signals. If we use a pulsed PD with a linear output characteristic, we will obtain a precision converter of voltage Ux into pulse duration Tx. In this converter, the analog input signal Ux is compared with the output signal Tx (more precisely, with the average value of the Tx pulse over a period of frequency Fo (Tx pulse area) with the average value of Ux over the same time). The presence of OOS and a large gain (Ku) of the low-pass filter provide high conversion accuracy and make it possible to reduce the requirements for the accuracy and stability of all circuit elements that are covered by OOS. The hardware implementation of the proposed circuit is not a difficult task; many different PLL integrated circuits are currently produced, for example, the CD4046 microcircuit (domestic analogues 1561GG1 and 564GG1) includes 2 types of PDs, a VCO and additional VCO control circuits. The 74NS4046 microcircuit, a functional analogue of the CD4046, has 3 types of PDs and can operate at higher frequencies. Figure 6 shows the hardware implementation of a low-pass filter for negative input voltages.

Fig.6 Low-pass filter circuit for negative input voltages.

The low-pass filter is made according to the circuit of a Proportional-Integrating filter on an op-amp (PI filter), which compares the average values ​​of the signals Ux and Tx over the frequency period Fo, resistors R1 and R2 determine the scale comparison factor. The product C1*R1 (integrator time constant Ti) determines the integrating effect of the filter, resistor R3 ensures the stability of the PIM circuit, and the ratio of R3 to R1 determines the proportional coefficient of the filter Kp. If the PD has an output characteristic in the region of positive voltages, then the input signal must have negative polarity. If the input signal is positive, then it is necessary to use a differential op-amp switching circuit, Fig. 7. The elements of the low-pass filter circuit must satisfy the following requirement: R3/R1 = R4/R2 and R1*C1 = R2*C2.

Fig.7 Low-pass filter circuit for positive input voltages.

The output signal of the low-pass filter controls the oscillator (VCO) so that the frequencies of the signals Fo and F1 are equal, and the phase shift between them is such that equality is satisfied.

Ux/R1 = (Up/R2)*Tx/T1, (1)

where Up is the amplitude of the Tx pulse (Up is the PD supply voltage);

T1 = 1/F1 period of the frequency at which the PLL operates.

The use of a PI filter makes the PLL system astatic in phase, which means that if R1=R2, then the steady-state value of the relative duration of the converter output pulses (Tx/T1) is determined only by the ratio Ux/Up and does not depend on the parameters of other circuit elements.

Ux/Up = Тх/Т1, (2)

Ux = Up* Tx/T1. (3)

In formula (3), the known quantities are the PD supply voltage (Up = 5v) and the PLL frequency period T1 = (1/16,000)*65,536 = 4.096 ms (the exact value of the frequency F1 = 244.140625 Hz). To measure the input voltage Ux, it is necessary to measure the pulse duration Tx (phase shift between the leading edges of the pulses F1 and F0) and substitute it into formula (3).

Methodology for calculating PLL circuit elements

The initial parameter is the frequency F1 at which the ADC with PLL should operate. To calculate the dynamic characteristics of control systems, the circular frequency (angular frequency) ω = 2π*F, in [rad/s], phase dimension ⱷ in [rad] is used. In steady state, when the frequencies are equal to F1=F0, the output characteristic of the PD (pin 15) of the D2 chip is shown in Figure 8.

Rice. 8 PD output characteristic.

FD conversion coefficient (pin 15 of chip D2) Kfd = Up/2 π [V/rad].

The VCO, which is part of the D2 chip, has 2 ways (2 inputs, pins 9 and 12) to control the output frequency F0:
- voltage control through the “VCON” input (pin 9), in addition to pin 11 “R1” a resistor is connected, the selection of which is described in the manual for the use of the PLL chip;
- current control through input “R2” (pin 12), usually this input is used to set the initial frequency of the VCO in the absence of voltage to the “VCON” input.

In the diagram of Figure 1, the 2nd method of controlling the VCO frequency is used, because in this case, a large range of output voltages of the low-pass filter is allowed, which is made on the op-amp chip D3A (AD823). The output voltage of the op-amp, which can vary from minus 15 V to +15 V, is converted by resistor R5 into the VCO frequency control current. By selecting the values ​​of the circuit elements (C2, R4 and R5), the VCO is adjusted in such a way that at zero output voltage of the low-pass filter (Ugun = 0 V), the VCO output frequency is Fo = 244 Hz ± 10%, and with Ugun = minus 5 V, the output frequency doubled Fo=488 Hz ±10%. This allows you to optimally use the entire linear range of the low-pass filter output voltage to compensate for all nonlinear characteristics of the circuit elements and maintain high accuracy of ADC conversion.

Rice. 9 VCO output characteristic.

PLL Dynamic Characteristics

To use PLL correctly, you need to know the static and dynamic characteristics of this device. On the Internet you can find a detailed output of the PLL transfer function for different designs of the low-pass filter. Figure 10 shows a block diagram of a linear model of an ADC with a PLL in steady state, when, after turning on the power, the transient process (searching and locking frequency F1) ended F0 = F1. Transfer functions of circuit elements are presented in operator form.

Rice. 10 Block diagram of a linear model of an ADC with a PLL in steady state.

Let's use the ready-made formula for the transfer function W(p) (mathematical description of the behavior of a dynamic system) of a PLL, in which a PI filter is applied. Transfer function (4) corresponds to a 2nd order oscillatory link:

where p is a complex variable that can be replaced by jω to construct the AFC of the device;

ωп = 2π*Fп – natural angular frequency of the PLL passband in [rad/s];

Fп – natural frequency of the PLL passband in [Hz] (transient frequency of the PLL circuit);

ξ – damping coefficient (attenuation of the transient process) of the PLL.

Figure 11 shows the logarithmic frequency response of the PLL in relative units of natural frequency for different values ​​of the damping coefficient ξ. Additionally, expressions are given that connect the parameters of the PLL transfer function with the parameters of the devices included in the analog signal to pulse duration converter circuit.

where Kfd is the constant of the FD transmission coefficient (V/rad);

Kgun – VCO transmission coefficient constant (rad/s*V);
Ti = R1*C1 – time constant of the PI filter integrator (c);
Кп = R3/R1 – proportional coefficient of the PI filter;

Fig. 11 Logarithmic frequency response of the 2nd order link.

The frequency response of the PLL corresponds to a 2nd order low-pass filter with a cutoff frequency ωп (rad/s) (transition frequency) and a slope (attenuation) of 20 dB per decade (6 dB/octave). When designing a converter with a PLL, it is necessary to select the device bandwidth ωп=2π*Fп and the damping coefficient ξ at frequencies above the cutoff frequency.

Let us determine the design parameters of a real ADC with PLL, which is shown in Figure 1.

Let's write down the parameters of the elements of a real PLL converter in literal expression (see Fig. 8 and Fig. 9): Kfd = Uр/2π; Kgun = 2πF0/Up; Ti = 1/F0 and F0= F1. Let us substitute the literal values ​​of the parameters into formulas (5) and (6), and obtain simple (for engineering assessment) formulas for calculating the dynamic characteristics of a converter with a PLL.

ωп = F0 [rad/s], (7)

Fп = F0/2π [Hz], (8)

ξ = Kn/2. (9)

Let us substitute the values ​​of a real PLL converter into formulas (8) and (9), and obtain the following values:

The bandwidth of the converter with PLL Fp = 244Hz/6.28 = 39 Hz;
- damping coefficient ξ = 1/2 = 0.5.

Using formulas (5) and (6), you can achieve the desired characteristics of the transient process of converting the input signal by changing the parameters of the circuit elements and the conversion frequency F0.

Results of testing the ADC layout with ATmega 16

To check the accuracy of the conversion of the input voltage Ux of the ADC with PLL, a V7-38 voltmeter was used, which displays the measured voltage in 5 decimal places with an error of no worse than 0.05% at the 2V limit, with a resolution of 0.1 mV and no worse than 0.1% at limit 20V with a resolution of 1mV.

The ADC layout with PLL has a measurement limit of ~ 6.5V (6553.5mV), the measured voltage is displayed on the LCD display (D5) in 5 decimal places with a resolution of 0.1mV. The choice of measurement limit is associated with a maximum decimal number of 65535, which corresponds to the maximum binary code value of the T1 timer-counter. The ADC reference voltage source is the supply voltage of the D2 chip (74HC4046), which in the breadboard is equal to Up = 5.029V (5,029.0 mV) (measured by V7-38). In order for the EMP code of the timer-counter T1 to be equal to 0.1 mV, it is necessary to fulfill condition (1), the maximum input current Uxmax / R1 must be balanced by the feedback circuit current Up / R2 (10).

65536 / R1 = 50290 / R2, (10)

R1 = R2* (65536/50290),

R1 = 1.303* R2,

R1 = 130.3 kOhm (see Fig. 1).

The diagram in Figure 1 shows a variable resistor RV1 = 1 kOhm, which is connected in series with R1 = 130 kOhm to fine-tune the ADC conversion scale factor. Table 1 and Figure 12 show the results of measuring the input voltage Ux using an ADC prototype with a PLL and a V7-38 voltmeter. The voltage Ux [V] was set from a laboratory power supply with a built-in voltmeter. The 1st, 2nd and 3rd columns of Table 1 show the readings of voltmeters without taking into account the sign (modulo) to simplify the comparison of the readings of Ux, V7-38 and ADC. In the 5th is the LCD display reading of the ADC, and in the 4th is the ADC reading, in which the error of 5 EMP associated with the initial offset of the front pulse F1 relative to the zero code of timer T1 is excluded. In the 6th and 7th columns of Table 1, the values ​​of the relative measurement errors in [%] of the power supply voltmeter relative to V7-38 and the ADC readings relative to V7-38, respectively. The LCD display readings are missing a comma after the 4th digit, which should appear after finalizing the MK program.

Table 1.

Fig. 12 Graphical representation of the results of testing an ADC with a PLL.

Attached to the letter there is a file “Photo ATsPF.xlsx” with photographs that simultaneously record the readings of the B7-38 and the ADC with PLL. The video clip about the experiment has a large memory capacity and can be sent to the editor if there is a request.

Analysis of the results of testing the ADC layout with ATmega 16

The results of checking the ADC layout show that the deviation of the ADC readings from the readings of the reference device V7-38 does not exceed 0.02%. This indicates a high linearity in the conversion of input voltage to pulse duration using a PLL.

The resolution of the ADC, when measuring voltages of more than 2 Volts, is 10 times higher than that of the V7-38 voltmeter (0.1 mV for the ADC and 1 mV for the V7-38 voltmeter).

The stability of the ADC readings does not exceed ±EMP, this indicates the low level of intrinsic noise of the method of converting voltage into pulse duration using a PLL.
In reality, in the ADC circuit with a PLL, two signals of different shapes are compared, a constant voltage and rectangular pulses, which can be represented as the sum of a constant voltage Up/2 and an infinite series of sinusoidal voltages (Fourier trigonometric series), the amplitude of which depends on the pulse duration Tx, and the frequency are multiples of the ADC conversion frequency (F1).
The filtering properties of PLLs are described in detail in the literature. The PLL is an ideal rejection filter for interference with frequencies that are multiples of the frequency at which the ADC operates. If the input signal Ux contains interference with frequencies F1, 2 F1, 3F1, etc., then they will be completely suppressed, because the average voltage (integral) of these sinusoids over the frequency period F1 is zero. The transfer function (11) of such a filter is shown in Fig. 13.

Fig. 13 Amplitude-frequency response of the filter (11).

(11)

This unique feature of the PLL is explained by the integrating property of the VCO, the output frequency of which is determined by the average voltage over the period of the operating frequency F1. Therefore, it is possible to compare at the input of the low-pass filter two signals of different shapes, a constant voltage Ux with a pulse signal Tx, while the noise in the pulse duration Tx is determined by interference with frequencies that are not a multiple of the operating frequency of the PLL. Considering that all internal processes of the MC and the ADC are synchronized by the frequency of the MC quartz oscillator, the pulse noise created by the operation of the MC does not affect the stability of the ADC readings. Therefore, the PLL ADC provides a resolution of 16 binary (5 decimal) bits. The resolution of the ADC built into the MK case is 10 binary (3 decimal) bits, the actual stability of the readings is 8 bits, which is 2 orders of magnitude worse than that of an ADC with a PLL.

Limitations that exist in ADCs with PLLs and how to eliminate them

The PD of the PLL chip (74NS4046) in the Frequency Detector (FD) mode, when the VCO is synchronized (frequency lock F1=F0), has an output characteristic in accordance with Figure 14.

Fig. 14 Output characteristic of 74NS4046 (pin 15) in black hole mode.

When the power is turned on (during the transient process), it is possible to synchronize the PLL circuit at subharmonics of the operating frequency, for example, F0 = 1.5*F1. Synchronization at subharmonics of the operating frequency occurs when the input signal Ux is on the boundary of the linear range of the PD output characteristic (Ux = ~ 0 or Ux = ~ Up).To eliminate such synchronization, the output characteristic of the PD in the frequency comparison mode must have a relay characteristic in accordance with Figure 15. In the phase comparison mode, it must correspond to Figure 8.

Fig. 15 Output, relay characteristic of PD for ADC with PLL in frequency comparison mode F1 and F0.

Ready-made PD microcircuits with this characteristic are not yet produced, so you can use a relay PD circuit, which was developed by the author and is given in the appendix to the article.

The second limitation is related to the operation of the voltage converter Ux into pulse duration Tx, code Ux=0V or Ux=Uр. The output characteristic of the PD (Figure 8) is periodic with a period of 2π, so it is necessary to reduce (for example, by 2%) the input voltage range in relation to the PD supply voltage [(Ux)max = 0.95Up] and shift the pulse duration reference point, for example , by 1% (see Fig. 16). When displaying the result of the ADC conversion using the program, take into account these changes in the output characteristics of the PD.

Fig. 16 ADC working area on the PD output characteristic when F1= F0.

Conclusion

The non-standard use of a PLL and MK system (without a built-in ADC) made it possible to create a cheap and precise ADC with high resolution and low noise levels.

The speed and resolution limits of an ADC with a PLL depend on the type of microcontroller.

If the ADC with PLL will be widely used by developers of electronic devices, then I propose the abbreviated name “ADCPF”.

The ADC is an ideal rejection filter for interference that is present in the input signal Ux if the interference frequency is equal to the operating frequency of the converter F1 or a multiple of this frequency (2F1, 3F1, etc.). If you synchronize the operating frequency of the MK with the network frequency of 50 Hz (using an RF generator, divider and other PLL system), then interference in the input signal Ux at frequencies multiples of 50 Hz will be suppressed, and the stability of the readings will increase.

Given that the ADC is an ideal noise rejection filter, this device can be used to digitally convert the output signal of, for example, an inductive sensor with a Phase Sensitive Rectifier (PSR) at the output. Typically, a low-pass filter is used to smooth out the ripple of the output voltage of the PV to the level of the required resolution of the ADC. This introduces a large delay into the signal monitoring system. If you use an AD converter at frequency F1 = Fmod, where Fmod is the modulation frequency (power supply to the inductive sensor), then a low-pass filter is not required; its function will be performed by the AD converter device itself.

Modern FPGA (Programmable Logic Integrated Circuit) technology is ideal for creating ADCs in a single package.

The author used the first application of ADPC, but without a microcontroller, which did not exist 30 years ago, to transmit high-precision analog signals through optocoupler isolation of telemetry channels of satellite equipment. An attempt to obtain a Certificate of Authorship for this technical solution was unsuccessful. The application for an Author's Certificate may still be in the State Public Library for Science and Technology.

Historical reference

The principle of phase-locked frequency control (synchronization) operates everywhere in nature. Synchronization was discovered by Huygens in the mid-17th century (1650–1680), who observed the adjustment of the periods of a clock hanging on one wall. The use of Phase Locked Loop (PLL) in electronic devices began in 1932, when the Frenchman H. de Belsiz was the first to describe a synchronous signal reception circuit, which was simpler and more elegant than the superheterodyne reception circuit then in use. This PLL circuit in Figure 17, in which a feedback signal causes a voltage-controlled oscillator to precisely adjust to the frequency of the incoming signal, is widely used in many modern information processing and transmission devices.

http://www.dsplib.ru/content/pll/pll.html http://physics.nad.ru/Physics/Cyrillic/harm_txt.htm
10. http://www.kit-e.ru/articles/elcomp/2003_8_92.php
11. Blekhman I.I. Synchronization in nature and technology.
12. “Electronics: past, present, future” (Translated from English, edited by Corresponding Member of the USSR Academy of Sciences V.I. Siforov [“Mir”; M., 1980 (296 pp.)].

MORDOVIA STATE UNIVERSITY

NAMED AFTER N.P. OGAREVA

Institute of Physics and Chemistry

Department of Radio Engineering

Laboratory work

Course: “Radioautomatics”

On the topic: “PHASE LOCKED FREQUENCY LOOPING”

Student of group 403 d/o Goncharov D.L.

Specialty 210601 "RESiK"

Checked by Pyanzin D.V.

Saransk 2014

1. General information.

A phase-locked loop (PLL) is an automatic control system that provides automatic control of the frequency of a controlled generator in signal receiving and processing devices in accordance with the frequency of the input signal and uses a phase detector as a measuring element.

PLL systems are used to adjust the local oscillator frequency in superheterodyne radio receivers, to isolate the carrier frequency in demodulators of message transmission systems, to implement coherent signal reception, to measure frequency using narrow-band tracking filters, to form highly stable oscillations in frequency synthesizers of various radio devices, etc. PLL systems can be implemented in analog and digital form.

A feature of the PLL system (in synchronization state) is zero static error in frequency, i.e. equality of oscillation frequencies of the adjusted oscillator (local oscillator) and the reference (input) oscillation
. At the same time, in electronic PLL systems there is a static phase control error, that is, a static difference in the oscillation phases of the tuned voltage-controlled oscillator (VCO) and the reference signal. PLL systems typically have a relatively narrow initial offset range over which they perform their trimming action. When analyzing the operation of a PLL system, the hold and capture modes are considered.

Holding mode is called steady-state equal frequency mode
, corresponding to the efficient operation of the PLL system with slow changes in the initial detuning. This refers to changes whose speed is much less than the speed of transient processes in the system.

The capture mode is the process that occurs when the initial detuning changes abruptly and ends with the establishment of the hold mode. A characteristic difference between these modes is that in the capture mode, transient processes play a significant role.

The main characteristics of PLL systems are the following:

Hold bar
- the region of initial VCO detuning, within which the PLL system effectively operates in hold mode.

Capture strip
- the region of initial VCO detuning, within which the PLL system effectively operates in capture mode.

Capture time t 3 is the time it takes for the PLL system to enter the synchronization mode, which significantly depends on the value of the initial detuning between the input oscillation frequency and the VCO oscillation frequency.

2. Operating principles of a phase-locked loop system.

The main elements of the structural diagram of a phase-locked loop system (Fig. 1) are: phase detector - PD, low-frequency filter - LPF, amplifier - US, control element UE and tunable (synchronized) generator - VCO.

Rice. 1. Block diagram of the PLL system.

One input of the PD phase detector receives a signal
, on the second - high-frequency oscillation
synchronized tunable generator. Between the PD output and the input of the control element in the feedback loop there is a low-pass filter and a DC amplifier. It is these two elements of the structural diagram that practically form the frequency response of the PLL system and determine its loop transmission coefficient. If the signal frequency ω c and the oscillation frequency at the VCO output ω g differ from each other by a constant value Δω, then the instantaneous value of the phase difference φ between them will be equal to:

Typically, an analog multiplier is used as a PD phase detector (Fig. 1), which has a low-pass filter at the output that passes only the difference frequency oscillation. Then at the output of this multiplier there will be an oscillation of the form:

Where
transmission coefficient of the phase detector (analog multiplier).

If we put the transmission coefficient of the low-pass filter in the passband K low-pass filter = 1, then the voltage at the input of the control element of the UE will be proportional to the cosine of the current phase shift between the oscillations:

Where
, k- feedback loop transmission coefficient.

The control voltage is used in the PLL to adjust the oscillator controlled by the VCO voltage. The change in frequency ω g will be determined by the change in phase shift φ(t).

Let's take a closer look at the operating modes of the PLL system.

Depending on the initial frequency difference ω n of the input oscillation ω C and the VCO frequency ω Г0 with an open feedback loop, the PLL system can be in different modes (Fig. 2). In this figure, the straight line Δω = ω n corresponds to an open feedback loop of the PLL system.

Rice. 2. Dependence of the difference between the frequencies of the input signal ω c and the VCO signal ω g on the value ω n.

When the initial detuning ω Н is greater than the holding band ΔΩ У, a beat mode is observed in the PLL system, which is characterized by the absence of equal frequencies of the VCO and the input signal, i.e. ω C ≠ ω G. In this mode, the phase difference between the input oscillation and the VCO oscillation is continuous increases, and the voltage U PD (t) at the output of the phase detector changes, representing an oscillatory voltage of variable frequency. The average beat frequency is less than the initial detuning ω H. If the initial detuning increases, then the average beat frequency asymptotically tends to ω H (Fig. 2). The presence of a low-pass filter at the output of the phase detector of the PD, all other things being equal, leads to a decrease in the amplitude of the beats compared to the case of considering a PLL system without a low-pass filter, i.e., to the difficulty of entering the system into a synchronization state. This is why in PLL systems with low-pass filters the capture band is always less than the hold band (see Fig. 2).

When the value |ω N | values ​​ΔΩ 3 /2 the average beat frequency tends to zero, i.e. after time t 3 the VCO frequency and the input signal frequency become the same, and the PLL system switches to capture mode. In practice, the capture band ΔΩ З (Fig. 2) is determined by the moment of synchronization of the frequencies of the VCO and the input signal when |ω Н | from large values ​​to small ones.

In the presence of synchronization and a change in detuning |ω Н | from zero value towards increase, it is obvious that the oscillation beats will be absent until the moment of synchronization failure at |ω Н |≈ ΔΩ У /2.